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Advance Microcontroller Bus Architecture and Advance Peripheral Bus

Dhanush. M1, Dr. Sunil T. D2, Dr. M. Z. Kurian3

1PG Student, Dept. of ECE.,

Sri Siddhartha Institute of Technology, Tumkur,

Karnataka, India.

2Associate professor, Dept. Of ECE.,

Sri Siddhartha Institute of technology, Tumkur, Karnataka, India.

3Head of the Department, Dept. Of ECE.,

Sri Siddhartha Institute of Technology, Tumkur,  Karnataka, India.


 Microelectronics is increasingly playing a major role in our lives in the current era of modern technology. The growth of microelectronics equipment increases the requirement for manufacturing its components and its usage, if manufacturing time reduces it results in amplifying the misfiring rate of the finished product. In order to overcome this problem, the technocrats evolve a technique called verification, a process that is a part of manufacturing microelectronics products. In the ratio of 100% about 30% of the work is finished on design and 70% is invested in verification. Which will increase the efficiency and accuracy of hardware design and verification are extremely valuable. This work gives a survey of AMBA AHB ARBITER, a component of advanced micro controller bus architecture high-performance bus used to control the data transformation between masters and slaves. This paper gives a concise idea related to AMBA AHB ARBITER and also discussed its arbitration mechanism and its features.

Keywords: AMBA (advanced microcontroller bus architecture), APB (advanced peripheral bus), SOC (system on chip), RTL (register transfer level).

  1. Introduction

In the development of system on chip (SOC) intellectual property (IP) cores are of first line of choice. IP blocks will communicate using complex protocols and they are pre-verified by different interconnection with an SOC. Approaches include to facilitate plug and play style IP reuse which includes the development of a few standard on-chip bus architectures they are core connect from IBM, AMBA from ARM. Intellectual property cores are register transfer level (RTL) codes which will do certain proper performance. Nowadays the essence of digital systems design hang on hardware description languages (HOLs) rather than schematic diagrams. RTL codes are well tested they must be ready for any use in SOC development.

An AMBA is an on-chip communication bus protocol, it was introduced by ARM in 1996. It has two components AHB/ASB and APB. The AHB connects on chip RAM and all other external devices which are connected to the busses such as high performance processer high band width external memory etc. It also  provides interface to the external bus. System bus provides interface between the AHB puts the address on bus followed by the data it also supports read and write operation.

The APB supports for the low frequency devices it has low power consumption and low band width application. The objective of this paper is to design and implement APB protocol to understand how read and write transfer between the master and slave and designing the protocol with UVM based. This paper explain on chip interconnection specification and standard which defines the connection and functional block of the SOC. The UVM recognizes the test cases and the environment performs the functionality testing and sends the result to the transaction in the packet and compares them. If the count of the packet, address and data in both slave and master are equal the transaction matches and the test cases are passed correctly.

  1. Literature survey

On chip communication protocol includes a CPU and supporting function such as oscillator, timers, serial i/o, analog i/o as well as keypad program memory in the form of flash and read/write memory on a integrated circuit computer systems are also embedded in a machine such as automobiles telephone etc., while some embedded system have minimal requirements for memory and programming length with no OS. Rather than having separate connection between each set of devices that need to interact, bus design employs a single data-signalling channel for number of devices. Rather than having a single set of wires from CPU, the data bus is used. The bus having the control, which could be a quite complicate in many asynchronous process which attempting to share the bus effectively, early computer buses were bundle ofwires that are effectively, early computer buses were bundle of wires that are directly connected to memory and other peripherals, and they were accessed by separate instruction and protocols.


The second generation of the bus system are separate the computer into two “words”. The memory and CPU on one side and various devices on other side with a bus controller between the devices. This allow the CPU to increase the speed without affecting the bus this also moves the data out of the CPU into cards and controller, so devices on bus could communicate each other without involving CPU this leads to better real world performance, but makes cards more complicated an increase in number of external devices start employing their own bus system, when disk is going to drive the devices it introduced plug-in mechanism, so computer has many slots on the bus these bus was introduced in third generation, they also provides a lot of flexibility in terms of physical connection.


  1. APB Design:


The APB is the member of the AMBA protocol family. This is used for low frequency application. It consumes low power and reduces interface complexity. Therefore it interfaces to the low bandwidth peripherals. All the signal transaction are synchronised with rising edge of the clock.



Figure 1: Block diagram of APB protocol


Figure 2: State diagram

The finite state machine is an abstract mathematical model of sequential function. Figure 2 represents the FSM APB operation shows state machine of APB operation.

  1. Verification:


Verification is a most important step in VLSI design flow to find the bug in RTL design at early stage in design process verification is time consuming process around 70% of time is consumed for verification. UVM is a standard methodology used for RTL verification. UVM consists of base library classes coded in system verilog by extending these base classes the verification engineer is able create new verification component. Figure 3 illustrate the UVM verification component used to verify APB.

Figure 3: UVM verification component


Sequence time: This component is extended from uvm_seqyence_item. This component randomizes address and data.

  • : Sequence is an object that contains behaviour for generating the stimulus, these are extended from uvm_sequence.
  • : Sequencer controls the flow of the data from the sequencer and driver derived from uvm_sequencer
  • : Driver receives individual sequence item from sequencer and drives it on the DUT interface. Virtual interface is declared in driver to connect DUT. It is derived from uvm_driver base class.
  • : Monitor samples the DUT interface and capture the information there in transaction. It is extended from uvm_monitor base class.
  • : Generates and monitor pin level transaction. It is derived from uvm_agent class. Sequencer, driver and monitor are the members of agent.

Score board: Score board is an analysis component that checks the behaviour of DUT. Score board uses analysis transaction from input monitor implemented inside agent.

  • : UVM environment is a hierarchical component that groups together verification component that are interrelated. Typical component that are usually instantiated inside the environment are agent, scoreboard, sequence item, sequence. It is derived from uvm_env base class.
  • test is the place holder for environment inherited from uvm component class. Derived from uvm_test base class.




The purpose of this paper is to provide a detailed overview of AMBA APB protocol. The bus is designed using verilog according to specification and verified using universal verification methodology.


  1. “Design and verification of advanced peripheral bus protocol using uvm” by Pavani Yammanuru, M. Amaranath
  2. “ Design and verification of AMBA APB protocol” international journal of computer application article entitled design and verification of AMBA APB protocol.
  3. “Design and verification analysis of APB3 protocol with coverage” by akhilesh kumar and richasinha international journal of advances in engineering & technology, Nov 2011
  4. AMBA specification
  5. ARM- an AMBA specification overview
  7. Virtual Socket Interface Alliance.
  8. ARM. Advanced micro-controller bus architecture specification. spec, 1999.
  9. Open Core Protocol Intel Partnership Association Inc. Open core protocol specification., Release 1.0, 2001.
  10. IBM. 32-bit processor local bus, architecture specifications.
  11. http://www-, version 2.9.
  12. J. Bergeron, “What is verification?” in writing Test benches: Functional verification of HDL models, 2nd . New York: Springer Science, 2003, ch.1, pp. 1-24.
  13. International Technology Roadmap for Semiconductor [online]. Available:

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